Tweet flexes about upgrading to x86, misunderstands x64 naming joke
Description
Screenshot of a dark-mode tweet UI. The profile picture shows a monochrome anime character, name reads “ronin” with a blue verification badge, handle “@seatedro”, timestamp “· 1d”. Tweet text: “shocking to me that most people are still on x64 machines when i'm already on an x86 machine” followed by a blank line and the standalone line “keep up”. The humor relies on confusing CPU architecture labels - thinking “x86” (historically 32-bit) is somehow newer or more advanced than “x64” (64-bit extension of the x86 family). Developers will recognize the playful misunderstanding of instruction-set naming conventions and the perennial meme of boasting about technical superiority while actually downgrading
Comments
25Comment deleted
Bragging you’re on x86 is adorable - nothing says “cutting-edge” like a 4 GB address space and a JVM running on PAE life-support
Wait until they discover the i286 crowd - we're so far ahead we've wrapped around and are approaching from behind
Ah yes, the classic 'upgrade' from 64-bit to 32-bit architecture - because who needs more than 4GB of addressable memory anyway? It's like bragging about migrating from Kubernetes back to manually SSH-ing into servers. Nothing says 'cutting edge' quite like PAE flags and the constant fear of hitting memory limits. Keep up indeed - just make sure you're running in the right direction
Announcing you’re “already on x86” is like bragging about moving to ILP32 - great cache density, but you just lost long mode, eight extra GPRs, and most modern distro support
Bragging you’re “already on x86” is like boasting prod still fits in a 32‑bit address space - adorable, right up until Chrome opens one tab
x86 in 2024: Peak optimization - half the bits, double the pointer arithmetic nostalgia
i stands for imaginary unit Comment deleted
Already using 128-bit pointers... Comment deleted
I use 512 bit vectors where u at Comment deleted
SIMD operations, regardless of their register width (which may easily be as large as 4096 bits these days), are used to process the very same 8 to 64-bit pieces of data as general-purpose scalar registers do. I was referring to pointers, which are handled by scalar registers and traditionally limited to 16, 32 and currently 64 bits, thus being able to address 64 kilobytes, 4 gigabytes and 16 exabytes of [virtual] memory. In some processor architectures, those pointers may be extended to descriptors that store extra metadata needed to protect memory access from programmatic errors and vulnerabilities; for example, if regular pointer occupies 64 bits, the corresponding descriptor may have 128 bits. That metadata can be handled by conventional 64-bit registers, but it is obviously faster when a hardware acceleration is implemented for this purpose — to minimize overhead the very same way as SIMD does for processing bulk data. Comment deleted
This thing really exists? It sounds obsolete because operating systems already do it on a program level. If it really does improve performance then it has to become a new standard Comment deleted
pac/bti on arm exists for a while already, but it is not about perf, its about preventing ROPs Comment deleted
program level does nothing as it is always way too easy to smash the stack even by one improperly handled byte Comment deleted
Regular memory protection (that one at the OS level) concerns page access — that is 4096-byte granularity at most, not to mention huge pages of 2 megabytes or more — at process, so that other programs / users cannot use memory that is not their. I was referring to memory protection that has byte or word granularity (for example, 1-byte granularity for object boundaries and 4-byte granularity for uninitialized values) that protects the program against itself — such as off-by-one index errors. It's not about performance — it's about security and debugging, because the program is trapped instantly the very moment it attempts incorrect action, rather than when the memory is corrupted so badly that it is nearly impossible to trace back to the root cause. When paired with memory tagging (e. g. "this word contains uninitialuzed data / numeric data / function address / memory descriptir") and implemented in CPU hardware, it provides bulletproif protection against most common programmatic errors, that the program itself cannot bypass, as descriptors and tags cannot be forged programmatically like regular pointers. it has to become the new standard It's not that simple, though. • The whole program must run in this mode, including all the libraries. • Many optimization tricks violate the strict access rules — for example, fast implementations of strlen() that analyze multiple bytes at once. • While some protections have near zero performance penalty, others may be expensive — for example, use-after-free protection against "zombie" references. • Each 128-bit descriptor uses twice as much memory than a regular 64-bit pointer, which exhausts L1 and L2 caches twice as fast. • There are tons of poorly written programs that store pointers in generic integer variables, falsely assuming that it is always possible to convert an integer number back to a pointer — that is not possible with descriptors, as type casting removes their tag that cannot be forged back later. • There are tons of poorly written programs that falsely assume that pointer size is the same as a corresponding integer number size — that is obviously not true for descriptors that store extra metadata beyond that of a pointer visible to application. As a consequence, most software that we use today and that would benefit the most from such kind of protection, can hardly be ported to secure mode, — bur rather the most critical programs with clean code, those that are worth huge efforts. Comment deleted
Thanks for clarification. I didn't know it is a separate layer of protection than OS level. I was a little bit puzzled when seeing discussions about large register size advantages when "larger means slower" in computer architecture. I thought that if this allows to transfer burdens of OS to CPU then it would rather pay off, but surely it is not that straightforward Comment deleted
https://www.arm.com/architecture/cpu/morello https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ Comment deleted
8086 is the future Comment deleted
Have you heard 'bout transistors? They say they are hot stuff Comment deleted
nah 64-bit access is already too wide Comment deleted
That's what big 64 wants you to believe Comment deleted
nah nintendo64 is awesome Comment deleted
that's a MIPS-based architecture, mostly 32-bit with 64-bit characteristics Comment deleted
x87 exists, but he's still on x86... Comment deleted
In My college they are using 88💀 Comment deleted
68k anyone? Comment deleted