The 'simplicity' of modern ARM architecture revealed
Description
A two-panel Wojak/Soyjak meme comparing Intel and Apple's ARM processors. In the top panel, a smug, bearded Wojak with glasses looks at the Intel logo and its specifications - '1152 instructions (yes, including AVX-512)' and a '5000 page reference manual' - and declares, 'This bloated legacy garbage needs to die already.' In the bottom panel, the same character, now an ecstatic, open-mouthed Soyjak, marvels at the ARM and Apple M4 logos, saying, 'OMG SO SIMPLE!!!!1!'. The joke lies in the specifications listed next to the M4 chip: '1697 instructions' and a '14,000 page reference manual,' which are significantly larger than Intel's. The meme satirizes the hypocrisy and trend-following in tech communities, where ARM-based chips like Apple Silicon are praised as being simple and modern (in the spirit of RISC - Reduced Instruction Set Computing), while the data presented shows they have become even more complex than the 'bloated' CISC (Complex Instruction Set Computing) architectures they are replacing
Comments
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Calling x86 'bloated' while celebrating a 14,000-page ARM manual is the hardware equivalent of rewriting a monolith in 50 microservices and calling it 'simplification'
Modern RISC: we didn’t kill complexity, we just moved it into a 14 000-page PDF - turns out your eyeballs are the new microcode
The real complexity isn't in the instruction count - it's explaining to management why your perfectly optimized AVX-512 code runs slower than naive scalar loops because Intel disabled it on consumer chips to segment the market
Ah yes, the classic 'RISC is simpler' narrative - until you realize ARM's quest for performance parity with x86 has spawned more instruction variants than a CISC architect's fever dream. Turns out when you need to compete with decades of x86 optimization, your 'reduced' instruction set grows extensions faster than a microservices architecture grows YAML files. The real kicker? That 14,000-page manual exists because ARM's 'simplicity' now requires documenting every NEON variant, SVE width, and cryptographic extension across a dozen different profiles. Intel's looking at this thinking 'at least our technical debt is honest about being technical debt.'
Measuring ISA simplicity by opcode count is like sizing microservice complexity by repo count - meanwhile the decoder, scheduler, and memory model are filing a 14,000-page incident report
ARM is “so simple” - it only takes 14,000 pages to explain why your lock-free queue that sailed on x86’s TSO now needs three fences and a prayer
x86: 1152 instructions for ultimate flexibility. ARM: 168 for 'simplicity.' Both manuals thicker than the spec they claim to simplify - RISC truly stands for 'Reference Increases Slightly.'
Isn't CISC just RISC+microcode? So what are the upsides to the Risc architecture? Can't we have a bunch of cores with CISC? Comment deleted
RISC is faster. Executing fully hardware implemented instruction is more efficient than fetching bunch of small instructions from memory Comment deleted
But isn't risc the one fetching a bunch of small instructions? Whereas with cisc, you fetch a complex instruction, decode it into small ones, and feed the pipeline. While it executes, you decode the next instruction, so the pipeline does not stall. In fact, less memory for instructions helps with fetching speed and caching Comment deleted
Its more like you fetch complex instruction and than fetches bunch of small instructions Comment deleted
In any case, I think microcode makes the risc vs cisc distinction unhelpful and misleading, and we should compare processors case by case Comment deleted
Wait, is it real?🙀 Comment deleted
But x86 is still bloated legacy garbage... Like they still start in 16bit real mode, am I right? The fact that you can't see it anymore because of EFI doesn't mean it's not there Comment deleted
That means arm is even bigger legacy bloat garbage cus they try to emulate the x86 in some ways Comment deleted
Well you see, apple therefore good Comment deleted
Does this instruction count include GPU, NPU and other modules, or is it just CPU? Comment deleted
"RISC vs CISC" is not about the number of instructions (as all instructions are there for a purpose), but rather about the number of varieties of each instruction (determined by operand types). Comment deleted
Can we call this function overloading in assembly? Comment deleted
Intel isn't pure CISC tbh. If it was like this things would be much worse than nowadays Comment deleted
Pipelines exist for all processors Comment deleted
Its definitely easier to implement but you lack in efficiency, its like C and C# Comment deleted
Thats why you never see x86 in mobile or microcontrollers Comment deleted
I don't think it's as simple Comment deleted
Breaking news: soyjak memes don't offer nuanced commentary on complex issues Comment deleted
Regarding x86 I' ve heard completely different claims: - Their architectural instruction count is 6000. - Their hidden (not published) instruction count is allegedly 50000. Of course, it all may depend on how you define "an instruction". Anyway, the data presented in this meme seems just plain wrong. Comment deleted
At least it doesn't self-destruct itself (and can't be used as water boiler) Comment deleted
And yeah, I know that Intel fixed that. And I don't give a fuck about that Comment deleted
Bug can be fixed But shame will be forever Comment deleted